From: Hugo Villeneuve <hugo@hugovil.com>
Date: Wed, 27 Nov 2013 05:16:45 +0000 (-0500)
Subject: Add tests for timers mode 0
X-Git-Tag: v2.0.0~43
X-Git-Url: http://gitweb.hugovil.com/?a=commitdiff_plain;h=6a014db0cd2fe5176f99f8ac7a54dabec76b5e70;p=emu8051.git

Add tests for timers mode 0
---

diff --git a/tests/Makefile.am b/tests/Makefile.am
index 3cdcf40..51a5814 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -7,7 +7,7 @@ SUFFIXES = .hex .asm
 TESTS = \
     opcodes
 
-check_PROGRAMS = mul1.hex mul2.hex div.hex orl.hex anl.hex mov.hex timer1.hex
+check_PROGRAMS = mul1.hex mul2.hex div.hex orl.hex anl.hex mov.hex timer0.hex timer1.hex
 
 mul1.hex: mul1.asm
 mul2.hex: mul2.asm
@@ -15,6 +15,7 @@ div.hex: div.asm
 orl.hex: orl.asm
 anl.hex: anl.asm
 mov.hex: mov.asm
+timer0.hex: timer0.asm
 timer1.hex: timer1.asm
 
 .asm.hex:
diff --git a/tests/timer0.asm b/tests/timer0.asm
new file mode 100644
index 0000000..5935e24
--- /dev/null
+++ b/tests/timer0.asm
@@ -0,0 +1,59 @@
+; Test program to verify correct emu8051 operation
+;
+; Test desc: timers
+; Test output: PC = $FFF0
+; Test output: SP = $60
+; Test output: R0 = $83
+; Test output: R1 = $17
+; Test output: R2 = $81
+; Test output: R3 = $02
+; Test output: TIMER0 = $7103
+; Test output: TIMER1 = $8005
+; Test output: TCON = $A0
+; Test output: TMOD = $00
+; Test output: PSW = $00
+
+TOS     EQU     60h     ; Adresse du dessus de la pile.
+
+        CSEG
+
+        ORG     0000h           ; Reset vector
+        MOV     SP,#TOS         ; Init stack pointer
+
+        MOV     TMOD,#00h       ; Init timers 0 and 1 as:
+                                ;   8-bit timer "TH" with "TL" as 5-bit prescaler
+                                ; incremented by the internal clock
+
+        ;;  First test: no overflow
+	MOV	TH0,#2
+	MOV	TL0,#55h        ; Set initial value of timer0 to $0255
+        CALL    DELAY
+
+        MOV     00h, TH0         ; Save value of timer 0
+        MOV     01h, TL0
+        MOV     02h, TH1         ; Save value of timer 1
+        MOV     03h, TL1
+        MOV     04h, TCON
+
+        ;;  Second test: overflow
+	MOV	TH0,#0F0h
+	MOV	TL0,#01h        ; Set initial value of timer0 to $F001
+	MOV	Th1,#0FFh
+	MOV	TL1,#03h        ; Set initial value of timer1 to $FF03
+        CALL    DELAY
+
+        LJMP    0FFF0h
+
+        ;; Loop of $1020 cycles
+DELAY:
+	MOV	A,#08h
+       	ORL     TCON,#50h	; Timer 0 and timer 1 ON.
+B2:
+	MOV	B,#0
+B1:
+	DJNZ	B,B1
+	DJNZ	ACC,B2
+        ANL     TCON,#0AFh      ; Stop both timers
+        RET
+
+        END